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DATA SHEET
MOS INTEGRATED CIRCUIT
PD72001-11, 72001-A8
MULTI-PROTOCOL SERIAL CONTROLLERS
DESCRIPTION
The PD72001-11 is an MPSC (Multi-Protocol Serial Controller) which is a general-purpose communication LSI equipped with two sets of bidirectional parallel/serial converter circuits for data communication. This controller has a transmitter function to convert the parallel data output by a data terminal into serial data and transmit this data to a data transmission system such as a modem, and a receiver function to convert the serial data output by the data transmission system into parallel data. The MPSC can be used with data communications equipment with a variety of communication modes such as the generally and widely used start-stop synchronization mode, and the HDLC mode which is used for high-speed communication. The PD72001-A8 is a low-voltage model. For this product, the following documents are separately available. Read these documents as well as this Data Sheet. * User's Manual (S12472E) * Application Notes
FEATURES
* Two sets of parallel/serial circuits supporting three modes: start-stop synchronization, character synchronization, and bit synchronization modes Easy application to a system supporting two or more communication protocols such as a protocol converter or ISDN terminal adapter * DPLL (Digital Phase Locked Loop), baud rate generator, and crystal oscillation circuit for transmission/reception clock Helps reduce cost by decreasing the number of external circuits * Many variations with power-saving features and small package size Easy application to portable terminals and high-accuracy portable terminals The features common to the PD72001-11 and 72001-A8 are explained as the features of the MPSC in this document.
Document No. S12184EJ7V0DS00 (7th edition) Date Published November 1997 N Printed in Japan

(I) (S12753E) (II) (On preparation) (III) (On preparation)
The information in this document is subject to change without notice.
The mark
shows major revised points.
(c)
1997
PD72001-11, 72001-A8
ORDERING INFORMATION
Part Number Package 40-pin plastic DIP (600 mil) 44-pin plastic QFP (10 x 10 mm) (resin thickness: 1.45 mm) 52-pin plastic QFP (14 x 14 mm) (resin thickness: 2.7 mm) 52-pin plastic QFJ (750 x 750 mil) 40-pin plastic DIP (600 mil) 44-pin plastic QFP (10 x 10 mm) (resin thickness: 1.45 mm) 52-pin plastic QFP (14 x 14 mm) (resin thickness: 2.7 mm)
PD72001C-11 PD72001G-11-22 PD72001GC-11-3B6 PD72001L-11 PD72001C-A8 PD72001G-A8-22 PD72001GC-A8-3B6
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PD72001-11, 72001-A8
SPECIFICATIONS
Item Part number Supply voltage System clock frequency Maximum transfer rate Process Internal circuit 5 V 10 % 11 MHz MAX. 2.2 Mbps CMOS Parallel/serial converter circuit: Full-duplex channel x 2 Transmit buffer : Double Receive buffer : Quadruple Interrupt control function DMA request signal output: 2 for transmission, 2 for reception Overrun error detection DPLL Baud rate generator Crystal oscillation circuit for transmission/reception clock generation Self-loopback test function Standby function General-purpose I/O pin: 4 pins x 2 Start-stop synchronization Character bit length: 5, 6, 7, 8 Stop bit length: 1, 1.5, 2 Clock rate: x1, x16, x32, x64 Parity generation, check Framing error detection Break generation, detection Operation mode: Mono-sync, Bi-sync, External sync Character bit length: 5, 6, 7, 8 SYNC character bit length: 6, 8 Character synchronization: Internal/external BCS (Block Check Sequence) generation, check: CRC-16 CRC-CCITT Parity generation, check SYNC character automatic transmission, detection, rejection Operation mode: HDLC (High-level Data Link Control) SDLC (Synchronous Data Link Control) SDLC Loop Flag transmission, detection Zero insertion, rejection Address field detection (1 byte) FCS (Frame Check Sequence) generation, detection Short frame detection Abort automatic transmission, detection Idle detection Go Ahead detection Transmit number data control Specifications
PD72001-11
3.3 V 0.3 V
PD72001-A8
8 MHz MAX. (at TA = -10 to +70 C) 7.14 MHz MAX. (at TA = -40 to +85 C) 1.6 Mbps (at TA = -10 to +70 C) 1.43 Mbps (at TA = -40 to +85 C)
Communication protocol
COP (Character Oriented Protocol)
BOP (Bit Oriented Protocol)
Processing data format
Encode/decode of NRZ (Non-Return to Zero) Encode/decode of NRZI (Non-Return to Zero Inverted) Encode/decode of FM (Frequency Modulation) Decode in Manchester mode
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PD72001-11, 72001-A8
PIN CONFIGURATION (Top View)
* 40-pin plastic DIP (600 mil) : PD72001C-11, PD72001C-A8
DCDA D7 D6 D5 D4 D3 D2 D1 D0 GND WR RD C/D B/A PRO PRI INTAK INT CTSB DCDB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
CTSA RXDA XI1A/STRXCA XI2A/SYNCA TRXCA TXDA RTSA DRQRXA RESET CLK VDD DRQTXA DTRA/DRQTXB DTRB/DRQRXB RTSB TXDB XI2B/SYNCB XI1B/STRXCB RXDB TRXCB
* 44-pin plastic QFP (10 x 10 mm) : PD72001G-11-22, PD72001G-A8-22
RTSB DTRB/DRQRXB DTRA/DRQTXB DRQTXA VDD VDD CLK RESET DRQRXA RTSA TXDA
44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22
TXDB XI2B/SYNCB XI1B/STRXCB RXDB TRXCB IC DCDB CTSB INT INTAK PRI
PRO B/A C/D RD WR GND GND D0 D1 D2 D3
IC: Internally Connected (Leave this pin unconnected)
4
TRXCA XI2A/SYNCA XI1A/STRXCA RXDA CTSA IC DCDA D7 D6 D5 D4
PD72001-11, 72001-A8
* 52-pin plastic QFP (14 x 14 mm) : PD72001GC-11-3B6, PD72001GC-A8-3B6
NC NC RTSA DRQRXA RESET CLK VDD VDD DRQTXA DTRA/DRQTXB DTRB/DRQRXB NC NC TXDA TRXCA XI2A/SYNCA XI1A/STRXCA RXCA CTSA IC DCDA D7 D6 D5 D4 D3 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26
RTSB TXDB XI2B/SYNCB XI1B/STRXCB RXDB TRXCB IC DCDB CTSB INT INTAK PRI PRO
NC : No Connection IC : Internally Connected (Leave this pin unconnected.) * 52-pin plastic QFJ (750 x 750 mil) : PD72001L-11
D3 D4 D5 D6 D7 DCDA NC CTSA RXDA XI1A/STRXCA XI2A/SYNCA TRXCA TXDA D2 NC D1 NC D0 GND GND WR RD C/D NC B/A NC 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 41 14 40 15 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33
NC D2 NC D1 D0 GND GND WR RD C/D B/A NC NC
NC RTSA DRQRXA NC RESET CLK VDD VDD DRQTXA DTRA/DRQTXB NC DTRB/DRQRXB NC
PRO PRI INTAK INT CTSB DCDB NC TRXCB RXDB XI1B/STRXCB XI2B/SYNCB TXDB RTSB
5
6
XI1B/STRXCB XI2B/SYNCB
BLOCK DIAGRAM
System CLK
TRXCB RTSB
DCDB
CTSB
RXDB
TXDB
CLK/Stby CLK Cont.
Ch.B
D7-0
DB Buf.
Internal Bus
RD WR C/D B/A RESET Cont. RD/WR
CR 0-5 10-15 Cont. Sign.
BRG -H,L
SR 12-15
CR/SR 8-9 0-3
SR0 4-7
RX Buf.
CR 6-7
TX Buf.
TXRX CLK BRG DPLL SR1-4 10-11
DRQRXA DRQTXA DTRB/DRQRXB DTRA/DRQTXB DMA Cont.
RXCLK TXCLK
TXRX CLK Cont.
TXRX Cont.
Transmitter
OSC Receiver
PD72001-11, 72001-A8
INT INTAK PRI PRO Interface Cont. INT Cont.
RTSA TRXCA XI1A/STRXCA XI2A/SYNCA DCDA CTSA RXDA TXDA
Ch.A
PD72001-11, 72001-A8
1. PIN FUNCTIONS
The functions of the MPSC can be broadly classified into "system interface functions" that control interfacing with the host system, and "transmission/reception functions" to transmit or receive data. This section explains the functions of the pins of the MPSC by classifying the pins into those related to system interfacing and those related to transmission and reception. Hereafter, "H" (voltage level satisfying VIH in the case of an input pin, or voltage level satisfying VOH in the case of an output pin) and "L" (voltage level satisfying VIL in the case of an input pin, or voltage level satisfying VOL in the case of an output pin) are used to indicate the input/output status of a pin.
1.1 Pins Related to System Interface
(1) VDD Supply voltage pin (2) GND GND pin (3) RESET ... Input This pin inputs a signal from an external device to reset the MPSC. When "L" is input to this pin for the duration of 2 clock cycles (2tCYK) or longer, the MPSC is reset (this is called system reset). As a result of system reset, the transmitter, receiver, and interrupt/DMA functions of the MPSC are disabled, and the TXD pin and general-purpose output pins go high. In this case, because all bits of the control register (CR) are also reset, CR must be set again if a system reset has been executed. Table 1-1 shows the status of each pin at system reset, in comparison with the pin status at channel reset (CR0: D5, D4, D3 = "0, 1, 1"). The MPSC automatically enters the standby mode at system reset, lowering the power consumption from that in the normal operation mode.
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PD72001-11, 72001-A8
Table 1-1. Pin Status at Reset
Pin Status Pin Name WR RD B/A C/D D7 to D0 INT INTAK PRI PRO DRQTXA DRQRXA DTRA/DRQTXB, DTRB/DRQRXB TXDA, TXDB RXDA, RXDB TRXCA, TRXCB XI1A/STRXCA XI1B/STRXCB XI2A/SYNCA XI2B/SYNCB RTSA, RTSB CTSA, CTSB DCDA, DCDB O I I "H" - - "H" - - O I I/O I "H" - Input status - "H" - Retains current status - I/O I I I I I/O O I I O O O O RESET (system reset) - - - - - High impedance - - Depends on PRI "L" "L" DTR function, "H" Channel reset - - - - - High impedance - - Depends on PRI "L" "L" Retains current status
I/O
Input status
Retains current status
- : Undefined (4) CLK (System Clock) ... Input This pin inputs the system clock. The input frequency must be five times that of the data transfer rate or higher. (5) WR (Write) ... Input This pin inputs a write control signal for control words and transmit data. This pin is active-low. (6) RD (Read) ... Input This pin inputs a read control signal for status and receive data. This pin is active-low. (7) B/A (Channel B/Channel A) ... Input This pin inputs a signal to select a channel to be accessed when data is written or read. When this pin is "L", channel A is selected; when it is "H", channel B is selected. (8) C/D (Control/Data) ... Input This pin inputs a signal that determines the type of the data on the data bus when the data is written or read.
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PD72001-11, 72001-A8
Table 1-2 shows the selection operations by WR, RD, B/A, and C/D. Table 1-2. MPSC Control Signals and Operations
WR L RD H B/A L H H L L H L H L H H L L H H L H L x x x x H H L C/D L Channel A Channel B Channel A Channel B Channel A Channel B Channel A Channel B High-impedance state or INTAK sequence Setting prohibited Reads status register Writes control register Reads receive data from RX buffer Operation Writes transmit data to TX buffer
x : Don's Care (9) D7 through D0 (Data Bus) ... I/O These pins constitute a three-state 8-bit bidirectional data bus. This data bus is connected to the data bus of the host processor to transfer control words, status, and transmit/receive data. (10) INT (Interrupt) ... Output (open drain) This pin outputs an interrupt request signal. If an interrupt occurs in the MPSC, it goes low (active). Because this is an open-drain output pin, it must be pulled up. (11) INTAK (Interrupt Acknowledge) ... Input This pin inputs a signal to acknowledge interrupt request signals issued by the MPSC. This pin is active-low. This pin is used when the vector mode (CR2A: D7 = "1") is selected, and must be pulled up to "H" when the nonvector mode (CR2A: D7 = "0") is selected. (12) PRI (Priority Input) ... Input This input pin is used for an interrupt generation request signal and for an output control signal for interrupt vectors. In the normal operation mode, this pin provides an interrupt generation control function. During the INTAK sequence, it provides an output control function for interrupt vectors. How this pin is used differs depending on the interrupt mode. (a) In vector mode (CR2A: D7 = "1") In the normal operation mode, the PRI pin is used to control generation of interrupts. When interrupt vector output mode of Type A-3 or Type B-2 (CR2A: D5, D4, D3 = "0, 1, 0" or "1, 0, 0") is selected, interrupts can be generated regardless of whether the PRI pin is "L" or "H". If any other interrupt vector output mode is selected, the PRI pin must be kept "L" to enable generation of interrupts. During the INTAK sequence, an interrupt vector is output if "L" is input to the PRI pin in any interrupt vector output mode, and output of the interrupt vector is disabled if "H" is input to PRI.
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PD72001-11, 72001-A8
(b) Non-vector mode (CR2A: D7 = "0") In this mode, the PRI pin controls only the generation of interrupts because the INTAK sequence is not used. If an interrupt vector output mode other than Type A-3 and Type B-2 is selected, generation of an interrupt signal is enabled if "L" is input to the PRI pin. The interrupt signal is not generated if "H" is input to PRI. If an interrupt daisy chain is configured, inputting "L" to this pin indicates that a device having a higher priority does not acknowledge interrupt processing or does not have an interrupt request, and only the MPSC with "L" input to its PRI pin can generate an interrupt. (13) PRO (Priority Output) ... Output This pin is used when an interrupt daisy chain is configured. This output pin is active-low, and controls generation of interrupts requests from a device with a lower priority. Usually, this pin is used along with the PRI pin, and its operation is as follows: When PRI = "H", PRO = "H" When PRI = "L", PRO goes "H" if there is an interrupt request, and goes "L" if there is no interrupt request. (14) DRQTXA (DMA Request TXA) ... Output This pin outputs a DMA request to a DMA controller. This pin is active-high. It goes "H" if the transmitter of channel A has entered the TX Buffer Empty status. The condition under which this pin goes "H" differs as follows depending on the setting of the CR1 and D2 bits. CR1: D2 = "0": The DRQTXA pin goes "H" when the transmitter has entered the TX Buffer Empty status after the first transmit data has been written. It does not go "H" when the transmitter has entered the TX Buffer Empty status after reset. CR1: D2 = "1": The DRQTXA pin goes "H" when the transmitter has entered the TX Buffer Empty status. This signal is reset when transmit data has been written to channel A. (15) DRQRXA (DMA Request RXA) ... Output This pin outputs a DMA request to a DMA controller. This pin is active-high and goes "H" if the receiver of channel A has entered the RX Character Available status. This signal is reset only when receive data has been read from channel A. (16) DTRA/DRQTXB (Data Terminal Ready A/DMA Request TXB) ... Output The function of this pin is changed as follows depending on the setting of CR2A: D1 and D0. (a) When CR2A: D1, D0 = "0, 0" or "0, 1" This pin functions as the DTRA pin. This pin is a general-purpose output pin and can be used to control a modem, etc. The operation of the DTRA pin is as follows: When CR5A: D7 = "0", DTRA = "H" When CR5A: D7 = "1", DTRA = "L" (b) When CR2A: D1, D0 = "1, 0" This pin functions as the DRQTXB output pin. The function of this pin is the same as the DRQTXA pin, except this pin is used with channel B. (17) DTRB/DRQRXB (Data Terminal Ready B/DMA Request RXB) ... Output The function of this pin changes as follows depending on the setting of CR2A: D1 and D0.
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PD72001-11, 72001-A8
(a) When CR2A: D1, D0 = "0, 0" or "0, 1" This pin functions as the DTRB output pin. The function of this pin is the same as the DTRA pin, except this pin is used with channel B. (b) When CR2A: D1, D0 = "1, 0" This pin functions as the DRQRXB output pin. The function of this pin is the same as the DRQRxA pin, except this pin is used with channel B. (18) CTSA (Clear to Send A) and CTSB (Clear to Send B) ... Input This pin is a general-purpose input pin and can be used to control a modem, etc. Changes in the status of this pin affect the latching operation of the E/S bit. When E/S INT is enabled (CR1: D0 = "1"), the E/S interrupt is generated. If the Auto Enable mode (CR3: D5 = "1") is set, the transmitter can be controlled by using the TX Enable bit (CR5: D3) and this pin. This is illustrated in Table 1-3. Table 1-3. Auto Enable Mode and CTS Pin
CTS Pin L H H or L TX Enable Bit 1 1 0 Transmitter Status Enabled Disabled Disabled
(19) DCDA (Data Carrier Detect A) ... Input DCDB (Data Carrier Detect B) ... Input These are general-purpose input pins and can be used to control a modem, etc. Changes in the status of this pin affect the latching operation of the E/S bit. When E/S INT is enabled (CR1: D0 = "1"), the E/S interrupt is generated. If the Auto Enable mode (CR3: D5 = "1") is set, the receiver can be controlled by using the RX Enable bit (CR3: D0) and this pin. This is illustrated in Table 1-4. Table 1-4. Auto Enable Mode and DCD Pin
DCD Pin L H H or L RX Enable Bit 1 1 0 Receiver Status Enabled Disabled Disabled
(20) RTSA (Request to Send A) ... Output RTSB (Request to Send B) ... Output These are general-purpose output pins and can be used to control a modem, etc. The operations of these pins differ depending on the setting of the operation protocol and the setting of the Auto Enable bit, as shown in Table 1-5.
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PD72001-11, 72001-A8
Table 1-5. Auto Enable Bit and RTS Pin
Function Protocol Start-stop synchronization 1
Auto Enable Bit 0
RTS Cont. Bit 0 1 When "0" from beginning If set to "1" once and then reset to "0" 1
RTS Pin Status H L H If "L" while All SentNote = "0", and "H" if All Sent = "1" L H L
COP/BOP
Don't Care
0 1
Note SR1: D2
1.2 Pins Related to Transmission/Reception
(1) TXDA (Transmit Data A) and TXDB (Transmit Data B) ... Output These pins output transmit data. (2) RxDA (Receive Data A) and RxDB (Receive Data B) ... Input These pins input receive data. (3) XI1A/STRXCA (Crystal Input 1A/Source of Transmit Receive Clock A) ... Input XI1B/STRXCB (Crystal Input 1B/Source of Transmit Receive Clock B) ... Input The functions of these pins change depending on the setting of CR15: D7. (a) When CR15: D7 = "0" These pins function as the STRXC pins, and input the transmission and reception clocks, or input source clocks to the internal BRG (Baud Rate Generator) and DPLL (Digital Phase Locked Loop). (b) When CR15: D7 = "1" These pins function as XI1 pins and connect one end of the crystal for transmission/reception clock source oscillation. (4) XI2A/SYNCA (Crystal Input 2A/Synchronization A) ... I/O XI2B/SYNCB (Crystal Input 2B/Synchronization B) ... I/O The functions of these pins change depending on the setting of CR15: D7. (a) When CR15: D7 = 0 These pins function as SYNC pins. The functions of the SYNC pins differ as shown in Table 1-6, depending on the setting of CR4. (b) When CR15: D7 = "1" These pins function as XI2 pins and connect one end of the crystal for transmission/reception clock source oscillation.
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PD72001-11, 72001-A8
Table 1-6. Functions of SYNC Pins and Setting of CR4 (when CR15: D7 = "0")
Operation Protocol Start-stop synchronization Synchronization Detection Mode SYNC Pin Function Input D7 x D6 CR4 D5 x D4 D3 0 1 1 D2 1 0 1 Function The SYNC pins function as general-purpose input pins. Changes in the status of these pin ("H" "L" or "L" "H") affect the latch operation of the Sync/Hunt bit (SR1: D4), and cause the E/S interrupt. If a SYNC character is detected in the receive character, the SYNC pins go "L" for the duration of 1RXC cycle. 0 0 The SYNC pins input a signal for establishing character synchronization. When these pins go "L" from "H", execution exits from the Hunt Phase and character synchronization is established. While SYNC input is "L", character synchronization is maintained. Assembling a receive character is started at the rising edge of the receive clock preceding the falling of the SYNC input. The SYNC pins do not function.
COP
Internal synchronization External synchronization
Output
x
0 0
0 1 1
Input
0
0
1
0
1
BOP
No function
x
1
0
x : Don't Care Caution If a pattern in which 1 bit ("0" or "1") is inserted in between the "Sync character assigned to CR7" and "Sync character assigned to CR6" is received while data is being assembled in the Bi-Sync mode, an "L" pulse of about 1 bit may be generated on the SYNC pin. If the Enter Hunt command is issued while this "L" pulse is present, the command is invalid. However, the recieve operation of the MPSC is not affected at all by the reception of this pattern. (5) TRXCA (Transmit Receive Clock A) ... I/O TRXCB (Transmit Receive Clock B) ... I/O (a) When CR15: D2 = "0" These pins input the transmit and receive clocks. They are used to supply external transmit and receive clocks. [Exception] If either CR15: D6, D5 = "0, 1" or D4, D3 = "0, 1", or both are set, the TRXCA and TRXCB pins function as input pins, even if CR15: D2 = "1". (b) When CR15: D2 = "1" These pins function as output pins. The source of the output clock can be selected from a crystal oscillation circuit, BRG, DPLL, or transmit clock, depending on the setting of CR15: D1, D0. Under the conditions explained in [Exception] in (a) above, they unconditionally serve as input pins, and the setting of CR15: D2, D1, D0 is invalid.
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An example of a system where the PD72001-11 is used for a terminal adapter for ISDN is shown below.
Terminal adapter for ISDN
2. SYSTEM CONFIGURATION EXAMPLE
PD72001-11 PD98201
HDLC SYNC ASYNC Dch S-I/F HDLC SYNC ASYNC Transformer ISDN circuit
Bch
Bus
PD72002-11
RS-232-C D/R HDLC SYNC ASYNC CPU (with DMAC) ROM RAM
PD72001-11, 72001-A8
Personal computer
PD72001-11, 72001-A8
3. ELECTRICAL SPECIFICATIONS
(1) PD72001-11 Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD VI VO TA Tstg Condition Ratings -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 -40 to +85 -65 to +150 Unit V V V C C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. DC Characteristics
PD72001-11 (TA = -40 to +85 C, VDD = 5 V 10 %)
Parameter High-level input voltage Symbol VIHC VIH Low-level input voltage VILC VIL High-level output voltage Low-level output voltage High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current Supply current VOH VOL ILIH ILIL ILOH ILOL IDD Condition CLK, STRXC, TRXC Other pins CLK, STRXC, TRXC Other pins IOH = -400 A IOL = 2.0 mA VI = VDD VI = 0 V VO = VDD VO = 0 V At 11 MHz In standby modeNote 20 MIN. 3.3 2.2 -0.5 -0.5 0.7 VDD 0.45 10 -10 10 -10 40 1 TYP. MAX. VDD + 0.5 VDD + 0.5 +0.6 +0.8 Unit V V V V V V
A A A A
mA mA
Note System clock Input pin
: 11 MHz : Inactive
* High-level input voltage : (VDD - 0.3 V) to (VDD + 0.5 V) * Low-level input voltage : 0 V to 0.3 V Output pin : Leave unconnected.
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PD72001-11, 72001-A8
Capacitance (TA = 25 C, VDD = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN CIO fC = 1 MHz Pins other than test pin: 0 V Condition MIN. MAX. 10 20 Unit pF pF
AC Characteristics
PD72001-11 (TA = -40 to +85 C, VDD = 5 V 10 %)
System interface:
Rated Value Parameter Clock cycle Clock high-pulse width Clock low-pulse width Clock rise time Clock fall time Address setup time (vs. RD ) Address hold time (vs. RD ) RD pulse width Address data output delay time Symbol tCYK tWKH tWKL tKR tKF tSAR tHRA tWRL tDAD TA = -10 to +70 C TA = -40 to +85 C RD data output delay time tDRD TA = -10 to +70 C TA = -40 to +85 C RD data float delay time Address setup time (vs. WR ) Address hold time (vs. WR ) WR pulse width Data setup time (vs. WR ) tFRD tSAW tHWA tWWL tSDW TA = -10 to +70 C TA = -40 to +85 C Data hold time (vs. WR ) Recovery time between RD and WR tHWA tRV 10 0 0 120 100 90 0 140 ns ns 1.5 V 3.0 V 3.0 V 1.5 V 0 0 120 100 110 100 110 85 ns ns ns ns ns ns Condition MIN. 90 40 40 MAX. 2 000 1 000 1 000 10 10 Unit ns ns ns ns ns ns ns ns ns
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PD72001-11, 72001-A8
Serial control:
Rated Value Parameter Transmit/receive data cycle STRXC, TRXC input clock cycle STRXC, TRXC input clock pulse width High Low Symbol tCYD tCYC tWCH tWCL TA = -10 to +70 C TA = -40 to +85 C STRXC, TRXC TXD delay time tDTCTD1 tDTCTD2 TRXC TXD delay time RXD setup time (vs. STRXC, TRXC ) RXD hold time (vs. STRXC, TRXC ) RXD TXD delay time tDTCTD3 tSRDRC tHRCRD tDRDTD1 tDRDTD2 TXD INT delay time TXD DRQTX delay time RXC RXC
Note Note
Condition
MIN. 5 90 40 40 45
MAX.
Unit tCYK ns ns ns
x1 mode, COP, BOP x16, 32, 64 mode TRXC is output When DPLL is not used When DPLL is not used ECHO BACK mode Without SDLC Loop delay TX INT mode TX DMA mode RX INT mode RX DMA mode 4 4 7 7 0 0 120
100 300 100
ns ns ns ns ns
100 100 6 6 11 11 120 120
ns ns tCYK tCYK tCYK tCYK ns ns
tDTDIQ tDTDDQ tDRCIQ tDRCDQ tDRDQ tDWDQ
INT delay time DRQRX delay time
RD DRQRX delay time WR DRQTX delay time
Note Of STRXC and TRXC, the one used as the receive clock. Interrupt control:
Rated Value Parameter INTAK low-pulse width INTAK high-pulse width PRI PRO delay time INT PRO delay time 2nd INTAK INT delay time Symbol tWIAL tWIAH tDPIPO tDIQPO tDIAIQ INT output level = 0.8 INT output level = 2.2 SR2B read RD INT delay time tDRDIQ INT output level = 0.8 INT output level = 2.2 PRI setup time (vs. INTAK ) PRI hold time (vs. INTAK ) PRI setup time (vs. INTAK ) PRI hold time (vs. INTAK ) INTAK data output delay time INTAK data float delay time tSPIIA1 tHIAPI1 tSPIIA2 tHIAPI2 tDIAD tFIAD 10 When vector output is disabled VNote VNote VNote VNote 0 20 20 20 120 85 -20 Condition MIN. 120 120 50 +50 120 300 150 300 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
When vector output is enabled
Note Measured value with 2-k pull-up resistor and 100-pF load capacitance connected
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PD72001-11, 72001-A8
Modem control:
Rated Value Parameter CTS, DCD, SYNC pulse width High Low Symbol tWMH tWML tDMIQ TSSYRC COP external synchronization 0 Condition MIN. 2 2 2 2 MAX. Unit tCYK tCYK tCYK tCYK
CTS, DCD, SYNC INT delay time STRXC, TRXC SYNC setup time
Communication control:
Rated Value Parameter Transmit enable command (WR , CTS ) TXD delay time Receive enable command (DCD ) setup time (vs. start bit, STRXC , TRXC of sync character)Note Receive enable command (DCD ) hold time (vs. STRXC , TRXC )Note Symbol tDTETD1 tDTETD2 tSRERC ASYNC, COP BOP 4 1 Condition MIN. MAX. 3 7 Unit tCYC tCYC tCYC
tHRCRE1 tHRCRE2
ASYNC COP
7 20tCYC + 8tCYK 3tCYC + 8tCYK 1 22 5 1 1
tCYK
tHRCRE3 Receive clock (STRXC, TRXC)Note hold time (vs. stop bit, MSB of CRC, MSB of end flag) Receive clock (STRXC, TRXC)Note
BOP
tHRDRC1 tHRDRC2 tHRDRC3 tSRCRD1 tSRCRD2
ASYNC COP BOP ASYNC COP, BOP
Bit tCYC tCYC Bit tCYC
setup time (vs. start bit, sync character)
Note Of STRXC and TRXC, the one used as the receive clock. Crystal oscillation and reset
Rated Value Parameter XI1 input cycle time RESET pulse width Symbol tCYX tWRSL Condition MIN. 90 2 MAX. 2000 Unit ns tCYK
Caution The system clock cycle in all modes must be five times that of the data rate.
18
PD72001-11, 72001-A8
AC Test Input/Output Waveform (except clock)
2.4 0.45
2.2 0.8
Test points
2.2 0.8
AC Test Clock Input Waveform
3.3 0.6 Test points 3.3 0.6
Load Condition
DUT CL = 100 pF
CL includes jig capacitance
Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, keep the load capacitance of this device to within 100 pF by inserting a buffer or by some other means. Remark DUT: Tested device
19
PD72001-11, 72001-A8
(2) PD72001-A8 Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature Symbol VDD VI VO TA Tstg Condition Ratings -0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 -40 to +85 -0 to +150 Unit V V V C C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. DC Characteristics (TA = -40 to +85 C, VDD = 3.3 V 0.3 V)
Parameter High-level input voltage Symbol VIHC VIH Low-level input voltage VILC VIL High-level output voltage Low-level output voltage High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current Supply current VOH VOL ILIH ILIL ILOH Condition CLK, STRXC, TRXC Other pins CLK, STRXC, TRXC Other pins IOH = -400 A IOL = 2.0 mA VI = VDD VI = 0 V VO = VDD MIN. 0.8 VDD 1.8 -0.5 -0.5 2.2 0.5 10 -10 10 TYP. MAX. VDD + 0.5 VDD + 0.5 0.15 VDD +0.6 Unit V V V V V V
A A A A
mA mA
ILOL
VO = 0 V
-10
IDD
At 8 MHz In standby modeNote
5
20 1
Note System clock Input pin
: 8 MHz (TA = -10 to +70 C)/7.14 MHz (TA = -40 to +85 C) : Inactive
* High-level input voltage : (VDD - 0.3 V) to (VDD + 0.5 V) * Low-level input voltage : 0 V to 0.3 V Output pin Capacitance (TA = 25 C, VDD = 0 V)
Parameter Input capacitance I/O capacitance Symbol CIN CIO fC = 1 MHz Pins other than test pin: 0 V Condition MIN. MAX. 10 20 Unit pF pF
: Leave unconnected.
20
PD72001-11, 72001-A8
AC Characteristics (TA = -40 to +85 C, VDD = 3.3 V 0.3 V) System interface:
Rated Value Parameter Clock cycle Symbol tCYK Condition TA = -10 to +70 C TA = -40 to +85 C Clock high-pulse width Clock low-pulse width Clock rise time Clock fall time Address setup time (vs. RD ) tWKH tWKL tKR tKF tSAR 1.5 V 2.2 V 2.2 V 1.5 V TA = -10 to +70 C TA = -40 to +85 C Address hold time (vs. RD ) tHRA TA = -10 to +70 C TA = -40 to +85 C RD pulse width tWRL TA = -10 to +70 C TA = -40 to +85 C Address data output delay time tDAD TA = -10 to +70 C TA = -40 to +85 C RD data output delay time tDRD TA = -10 to +70 C TA = -40 to +85 C RD data float delay time Address setup time (vs. WR ) Address hold time (vs. WR ) tFRD tSAW tHWA TA = -10 to +70 C TA = -40 to +85 C WR pulse width tWWL TA = -10 to +70 C TA = -40 to +85 C Data setup time (vs. WR ) tSDW TA = -10 to +70 C TA = -40 to +85 C Data hold time (vs. WR ) tHWD TA = -10 to +70 C TA = -40 to +85 C Recovery time between RD and WR tRV TA = -10 to +70 C TA = -40 to +85 C 10 0 0 5 150 155 120 125 0 5 180 190 ns ns ns ns 0 5 0 5 150 155 120 125 120 125 120 ns ns ns ns ns ns ns MIN. 125 140 50 50 MAX. 2000 2000 1000 1000 10 10 Unit ns ns ns ns ns ns ns
21
PD72001-11, 72001-A8
Serial control:
Rated Value Parameter Transmit/receive data cycle STRXC, TRXC input clock cycle Symbol tCYD tCYC TA = -10 to +70 C TA = -40 to +85 C STRXC, TRXC input clock pulse width tWCL Low level tWCH High level TA = -10 to +70 C TA = -40 to +85 C TA = -10 to +70 C TA = -40 to +85 C STRXC, TRXC delay time tDTCTD1 x1 mode, COP, BOP tDTCTD2 x16, 32, 64 mode TA = -10 to +70 C TA = -40 to +85 C TA = -10 to +70 C TA = -40 to +85 C TRXC TxD delay time RXD setup time (vs. STRXC, TRXC ) tDTCTD3 tSRDRC TRXC is output When DPLL is not used RXD hold time (vs. STRXC, TRXC ) tHRCRD When DPLL is not used RXD TXD delay time tDRDTD1 tDRDTD2 TXD INT delay time TXD DRQTX delay time RxC RxC
Note Note
Condition
MIN. 5 125 140 50 55 60 65
MAX.
Unit tCYK
DC DC DC DC DC DC 140 145 300 305
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0 TA = -10 to +70 C TA = -40 to +85 C TA = -10 to +70 C TA = -40 to +85 C 0 5 140 145
100
ECHO BACK mode Without SDLC Loop delay TX INT mode TX DMA mode RX INT mode RX DMA mode 4 4 7 7
100 100 6 6 11 11 140 140
ns ns tCYK tCYK tCYK tCYK ns ns
tDTDIQ tDTDDQ tDRCIQ tDRCDQ tDRDQ tDWDQ
INT delay time DRQRX delay time
RD DRQRX delay time WR DRQTX delay time
Note Of STRXC and TRXC, the one used as the receive clock.
22
PD72001-11, 72001-A8
Interrupt control:
Rated Value Parameter INTAK low-pulse width INTAK high-pulse width PRI PRO delay time INT PRO delay time 2nd INTAK INT delay time Symbol tWIAL tWIAH tDPIPO tDIQPO tDIAIQ INT output level = 0.8 INT output level = 1.8 SR2B read RD INT delay time tDRDIQ INT output level = 0.8 VNote VNote VNote -20 Condition MIN. 150 150 50 +50 120 300 170 180 350 0 20 When vector output is disabled TA = -10 to +70 C TA = -40 to +85 C INTAK data output delay time INTAK data float delay time tDIAD tFIAD 10 20 20 25 120 130 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TA = -10 to +70 C TA = -40 to +85 C
INT output level = 1.8 VNote PRI setup time (vs. INTAK ) PRI hold time (vs. INTAK ) PRI setup time (vs. INTAK ) PRI hold time (vs. INTAK ) tSPIIA1 tHIAPI1 tSPIIA2 tHIAPI2 When vector output is enabled
Note Measured value with 2-k pull-up resistor and 100-pF load capacitance connected Modem control:
Rated Value Parameter CTS, DCD, SYNC pulse width High Low Symbol tWMH tWML tDMIQ tSSYRC COP external synchronization 0 Condition MIN. 2 2 2 2 MAX. Unit tCYK tCYK tCYK tCYK
CTS, DCD, SYNC INT delay time STRXC, TRXC SYNC setup time
23
PD72001-11, 72001-A8
Communication control:
Rated Value Parameter Transmit enable command (WR , CTS ) TXD delay time Receive enable command (DCD ) setup time (vs. start bit, STRXC , TRXC of sync character)Note Receive enable command (DCD ) hold time (vs. STRXC , TRXC )Note Symbol tDTETD1 tDTETD2 tSRERC ASYNC, COP BOP 4 1 Condition MIN. MAX. 3 7 Unit tCYC tCYC tCYC
tHRCRE1 tHRCRE2
ASYNC COP
7 20 tCYC + 8tCYK 3tCYC + 8tCYK 1 22 5 1 1
tCYK
tHRCRE3 Receive clock (STRXC, TRXC)Note hold time (vs. start bit, MSB of CRC, MSB of end flag) Receive clock (STRXC, TRXC)Note setup time (vs. start bit, sync character)
BOP
tHRDRC1 tHRDRC2 tHRDRC3 tSRCRD1 tSRCRD2
ASYNC COP BOP ASYNC COP, BOP
Bit tCYC tCYC Bit tCYC
Note Of STRXC and TRXC, the one used as the receive clock. Crystal oscillation and reset:
Rated Value Parameter XI1 input cycle time Symbol tCYX Condition TA = -10 to +70 C TA = -40 to +85 C RESET pulse width tWRSL MIN. 125 140 2 MAX. 1000 1000 tCYK Unit ns
Caution The system clock cycle in all modes must be five times that of the data rate.
24
PD72001-11, 72001-A8
AC Test Input Waveform (except clock)
2.2 0.5
1.8 0.6
Test points
1.8 0.6
AC Test Clock Input Waveform
0.8 VDD 0.15 VDD Test points 0.8 VDD 0.15 VDD
Load Condition
DUT CL = 100 pF
CL includes jig capacitance
Caution If the load capacitance exceeds 100 pF due to the configuration of the circuit, keep the load capacitance of this device to within 100 pF by inserting a buffer or by any other means. Remark DUT: Tested device
25
PD72001-11, 72001-A8
Clock Timing
tCYK tWKH CLK tKF tKR tWKL
Read Cycle Timing
C/D, B/A tSAR tWRL RD tDRD D7-0 Hi-Z tDAD tFRD Hi-Z tHRA
Write Cycle Timing
C/D, B/A tSAW tWWL WR tSDW D7-0 Hi-Z tHWD Hi-Z tHWA
Read/Write Cycle Timing (except transfer of transmit/receive data)
tRV RD, WR
26
PD72001-11, 72001-A8
Transmit Cycle Timing
tCYC tWCL STRXCA/B TRXCA/B tDTCTD3 TXDA/B tDTDIQ INT tDTDDQ DRQTXA/B tCYD tWCH
Receive Cycle Timing
tCYC tWCL STRXCA/B TRXCA/B tSRDRC RXDA/B tDRCIQ INT tDRCDQ DRQRXA/B tHRCRD tCYD tWCH
27
PD72001-11, 72001-A8
Transmitter Enable Timing
CTS
WR tDTETD1, tDTETD2 TXD
Receiver Enable Timing
STRXC TRXC
RXD tSRERC DCD
Note
Note LSB of the first receive data (SYNC, flag) Receive Clock Setting Timing a. In ASYNC mode
STRXC TRXC tSRCRD1 RXD Start bit
b. In COP/BOP mode
STRXC TRXC tSRCRD2 RXD Note
Note LSB of sync pattern (SYNC, flag)
28
PD72001-11, 72001-A8
DCD Timing, Receive Clock Hold Timing a. In ASYNC mode
1 2
tDCY
STRXC TRXC tHRDRC1 RXD Stop bit tHRCRE1 DCD
b. COP/BOP mode
STRXC TRXC tHRDRC2, tHRDRC3 RXD Note tHRCRE2, tHRCRE3 DCD
Note This bit is the MSB of BCS in the COP mode and MSB of the end flag in the BOP mode. In ECHO BACK Mode and LOOP Mode
RXD tDRDTD1, tDRDTD2 TXD
29
PD72001-11, 72001-A8
DMA Cycle Timing
DRQTXA/B DRQRXA/B tDRDQ RD tDWDQ WR
PRO Output Timing
PRI
INT tDPIPO PRO tDIQPO
INTAK Cycle Timing
PRI (when vector output is disabled) tSPIIA2 PRI (when vector output is enabled) tSPIIA1 INTAK tWIAL RD tDIAD D7-0 Hi-Z tFIAD Hi-Z tWIAH tHIAPI1 tHIAPI2
tDIAIQ INT tDRDIQ
30
PD72001-11, 72001-A8
E/S Timing
tWML CTSA/B, DCDA/B, SYNCA/B tDMIQ INT tWMH
SYNC Input Timing (external synchronization mode)
STRXCA/B TRXCA/B Last Bit of SYNC Character SYNCA/B
Note
1st Bit of Data Character
tSSYRC
Note SYNCA/B input must be cleared to "0" at the rising edge of RXC two clock cycles after the last bit of the SYNC character. XI1 Input Timing
tCYX
XI1
RESET Pulse
RESET
tWRSL
31
PD72001-11, 72001-A8
4. PACKAGE
40PIN PLASTIC DIP (600 mil)
40 21
1
A I
20
K L
J
H G F D N
M
M C B
R
NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 53.34 MAX. 2.54 MAX. 2.54 (T.P.) 0.500.10 1.2 MIN. 3.60.3 0.51 MIN. 4.31 MAX. 5.72 MAX. 15.24 (T.P.) 13.2 0.25 +0.10 -0.05 0.25 0~15
INCHES 2.100 MAX. 0.100 MAX. 0.100 (T.P.) 0.020 +0.004 -0.005 0.047 MIN. 0.1420.012 0.020 MIN. 0.170 MAX. 0.226 MAX. 0.600 (T.P.) 0.520 0.010 +0.004 -0.003 0.01 0~15 P40C-100-600A-1
32
PD72001-11, 72001-A8
44 PIN PLASTIC QFP ( 10)
A B
33 34
23 22
detail of lead end
D
C
S
44 1
12 11
F
G
H
I
M
J K
P
N L
M
55
Q
P44G-80-22-2
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q S
MILLIMETERS 13.6 0.4 10.0 0.2 10.0 0.2 13.6 0.4 1.0
1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2
INCHES
0.535+0.017 -0.016 0.394+0.008 -0.009 0.394+0.008 -0.009 0.535+0.017 -0.016 0.039 0.039 0.014+0.004 -0.005 0.006 0.031 (T.P.) 0.071+0.008 -0.009 0.039+0.009 -0.008 0.006+0.004 -0.003 0.006 0.057+0.005 -0.004 0.002 0.002 0.065 MAX.
1.0 0.2
0.15+0.10 -0.05
0.15
1.45 0.1 0.05 0.05
1.65 MAX.
33
PD72001-11, 72001-A8
52 PIN PLASTIC QFP ( 14)
A B
39 40
27 26
detail of lead end
D
C
S Q
52 1
14 13
F
G
H
IM
J K
P
N
L
M
P52GC-100-3B6,3BH-2 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.40 0.10 0.20 1.0 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.016+0.004 -0.005 0.008 0.039 (T.P.) 0.071+0.008 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
34
55
PD72001-11, 72001-A8
52 PIN PLASTIC QFJ ( 750 mil)
A B
F
E
J
G
H
T K M NM P Q
I
U
D
C
52 1
P52L-50A1-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K M N P Q T U MILLIMETERS 20.1 0.2 19.12 19.12 20.1 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 MIN. 3.4 1.27 (T.P.) 0.40 0.10 0.12 18.04 0.20 0.15 R 0.8 0.20+0.10 -0.05 INCHES 0.791 +0.009 -0.008 0.753 0.753 0.791 +0.009 -0.008 0.076+0.007 -0.006 0.024 0.173+0.009 -0.008 0.110+0.009 -0.008 0.035 MIN. 0.134 0.050 (T.P.) 0.016+0.004 -0.005 0.005 0.710+0.009 -0.008 0.006 R 0.031 0.008+0.004 -0.002
35
PD72001-11, 72001-A8
5. RECOMMENDED SOLDERING CONDITIONS
It is recommended to solder this product under the following conditions. For details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Surface mount type * PD72001G-11-22 : 44-pin plastic QFP (10 x 10 mm)
PD72001G-A8-22 : 44-pin plastic QFP (10 x 10 mm)
Recommended Condition Symbol IR35-107-2
Soldering Method Infrared reflow
Soldering Condition Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.), Number of times: 2 MAX., Number of days: 7Note (After that, prebaking for 10 hours at 125 C is necessary.) Products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. Package peak temperature: 215 C, Time: 40 seconds MAX. (200 C MIN.), Number of times: 2 MAX., Number of days: 7Note (After that, prebaking for 10 hours at 125 C is necessary.) Products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. Solder bath temperature: 260 C MAX., Time: 10 seconds MAX., Number of times: 1, Preheating temperature: 120 C MAX. (package surface temperature), Number of days: 7Note (After that, prebaking for 10 hours at 125 C is necessary.) Products other than in heat-resistance trays (such as those packaged in a magazine, taping, or non-heat-resistance tray) cannot be baked while they are in their package. Pin temperature: 300 C MAX., Time: 3 seconds MAX. (per side of device)
VPS
VP15-107-2
Wave soldering
WS60-107-1
Partial heating
--
Note The number of days the product can be stored at 25 C, 65 % RH MAX. after the dry pack has been opened. Caution Do not use two or more soldering methods in combination (except partial heating).
36
PD72001-11, 72001-A8
* PD72001GC-11-3B6 : 52-pin plastic QFP (14 x 14 mm)
PD72001GC-A8-3B6: 52-pin plastic QFP (14 x 14 mm)
Recommended Condition Symbol IR35-00-3
Soldering Method Infrared reflow
Soldering Condition Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.), Number of times: 3 MAX. Package peak temperature: 215 C, Time: 40 seconds MAX. (200 C MIN.), Number of times: 3 MAX. Solder bath temperature: 260 C MAX., Time: 10 seconds MAX., Number of times: 1 Preheating temperature: 120 C MAX. (package surface temperature) Pin temperature: 300 C MAX., Time: 3 seconds MAX. (per side of device)
VPS
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
--
Caution Do not use two or more soldering methods in combination (except partial heating). * PD72001L-11: 52-pin plastic QFJ (750 x 750 mil)
Recommended Condition Symbol VP15-00-1
Soldering Method VPS
Soldering Condition Package peak temperature: 215 C, Time: 40 seconds MAX. (200 C MIN.), Number of times: 1 Pin temperature: 300 C MAX., Time: 3 seconds MAX. (per side of device)
Partial heating
--
Through-hole type * PD72001C-11 : 40-pin plastic DIP (600 mil)
PD72001C-A8: 40-pin plastic DIP (600 mil)
Soldering Method Wave soldering (pins only) Partial heating Soldering Condition Solder bath temperature: 260 C MAX., Time: 10 seconds MAX. Pin temperature: 300 C MAX., Time: 3 seconds MAX. (per pin)
Caution When soldering this product using of wave soldering, exercise care that the solder does not come in direct contact with the package.
37
PD72001-11, 72001-A8
[MEMO]
38
PD72001-11, 72001-A8
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
39
PD72001-11, 72001-A8
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed : PD72001-A8 License needed : PD72001-11
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
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